AWESpice: a general tool for the accurate and efficient simulation of interconnect problems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Stable and efficient reduction of substrate model networks using congruence transforms
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Using articulation nodes to improve the efficiency of finite-element based resistance extraction
DAC '96 Proceedings of the 33rd annual Design Automation Conference
TICER: realizable reduction of extracted RC circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Guaranteed passive balancing transformations for model order reduction
Proceedings of the 39th annual Design Automation Conference
RCLK-VJ network reduction with Hurwitz polynomial approximation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Branch Merge Reduction of RLCM Networks
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Realizable parasitic reduction for distributed interconnects using matrix pencil technique
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
A wideband hierarchical circuit reduction for massively coupled interconnects
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Digital Circuit Optimization via Geometric Programming
Operations Research
Hierarchical Krylov subspace reduced order modeling of large RLC circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Hierarchical Krylov subspace based reduction of large interconnects
Integration, the VLSI Journal
Efficient methods for large resistor networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Large-scale flip-chip power grid reduction with geometric templates
Proceedings of the Conference on Design, Automation and Test in Europe
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We propose a realizable RCLK-in-RCLK-out parasitic reduction technique. The method employs generalized Y-Δ transformation. In our method, admittances are kept in their original rational forms of s, and their orders are reduced by truncating high-order terms. Therefore reduced admittances match the low-order terms in exact admittances. First-order realization of admittances is guaranteed, and higher-order realization is achieved by template optimization using Geometric Programming. The algorithm uniquely uses common-factor identification and cancelation operations to make Y-Δ transformation numerically stable. The experiment shows that our method can achieve higher reduction ratio than TICER and comparable simulation results with PRIMA.