Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A realizable driving point model for on-chip interconnect with inductance
Proceedings of the 37th Annual Design Automation Conference
TICER: realizable reduction of extracted RC circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Realizable parasitic reduction using generalized Y-Δ transformation
Proceedings of the 40th annual Design Automation Conference
Realizable RLCK circuit crunching
Proceedings of the 40th annual Design Automation Conference
Vector potential equivalent circuit based on PEEC inversion
Proceedings of the 40th annual Design Automation Conference
Including Higher-Order Moments of RC Interconnections in Layout-to-Circuit Extraction
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A General S-Domain Hierarchical Network Reduction Algorithm
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Branch Merge Reduction of RLCM Networks
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of interconnect networks using complex frequency hopping (CFH)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a novel compact passive modeling technique for high-performance RF passives and interconnects modeled as high-order RLCM circuits. The new method is based on a recently proposed general s-domain hierarchical modeling and analysis method. In this work, we first apply state-space based optimization technique to enforce passivity on the hierarchical model order reduced admittance matrix. To realize the passivity-enforced admittance, we propose a general multi-port network realization method based on relaxed one-port network synthesis technique based on Foster's canonical form. The resulting modeling algorithm leads to general SPICE-in and SPICE-out multi-port passive realization of any linear passive networks with easily controlled model accuracy and complexity. The experimental results on a number of PEEC modeled bus lines circuits demonstrate the effectiveness of the proposed algorithm.