Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
IES3: a fast integral equation solver for efficient 3-dimensional extraction
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
RF microelectronics
TICER: realizable reduction of extracted RC circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interconnect Analysis and Synthesis
Interconnect Analysis and Synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Realizable parasitic reduction using generalized Y-Δ transformation
Proceedings of the 40th annual Design Automation Conference
Realizable RLCK circuit crunching
Proceedings of the 40th annual Design Automation Conference
Vector potential equivalent circuit based on PEEC inversion
Proceedings of the 40th annual Design Automation Conference
Including Higher-Order Moments of RC Interconnections in Layout-to-Circuit Extraction
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Hierarchical Modeling and Simulation of Large Analog Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A General S-Domain Hierarchical Network Reduction Algorithm
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Branch Merge Reduction of RLCM Networks
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Canonical symbolic analysis of large analog circuits with determinant decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of interconnect networks using complex frequency hopping (CFH)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Compact Reduced Order Modeling for Multiple-Port Interconnects
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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This paper proposes a novel wideband modeling technique for high-performance RF passives and linear(ized) analog circuits. The new method is based on a recently proposed s-domain hierarchical modeling and analysis method [27]. Theoretically, we show that the s-domain hierarchical reduction is equivalent to implicit moment matching around s = 0, and that the existing hierarchical reduction method by one-point expansion is numerically stable for general tree-structured circuits. Practically, we propose a hierarchical multi-point reduction scheme for high-fidelity, wideband modeling of general passive or active linear circuits. A novel explicit waveform matching algorithm is proposed for searching the dominant poles and residues from different expansion points based on the unique hierarchical reduction framework. Experimental results with large analog circuits, on-chip spiral inductors are presented to validate the proposed method.