Efficient techniques for modeling chip-level interconnect, substrate and package parasitics
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources
Proceedings of the 37th Annual Design Automation Conference
Passive model order reduction of multiport distributed interconnects
Proceedings of the 37th Annual Design Automation Conference
Realizable reduction for RC interconnect circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Practical considerations for passive reduction of RLC circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interconnect parasitic extraction in the digital IC design methodology
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Efficient and passive modeling of transmission lines by using differential quadrature method
Proceedings of the conference on Design, automation and test in Europe
An analytic calculation method for delay time of RC-class interconnects
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Balanced truncation with spectral shaping for RLC interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Novel interconnect modeling by using high-order compact finite difference methods
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Early probabilistic noise estimation for capacitively coupled interconnects
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
A factorization-based framework for passivity-preserving model reduction of RLC systems
Proceedings of the 39th annual Design Automation Conference
Model order reduction for strictly passive and causal distributed systems
Proceedings of the 39th annual Design Automation Conference
Remembrance of circuits past: macromodeling by data mining in large analog design spaces
Proceedings of the 39th annual Design Automation Conference
Aggressive crunching of extracted RC netlists
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Mixed-Technology System-Level Simulation
Analog Integrated Circuits and Signal Processing
Hurwitz stable reduced order modeling for RLC interconnect trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Fast analysis and optimization of power/ground networks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Practical considerations in RLCK crosstalk analysis for digital integrated circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Signal integrity management in an SoC physical design flow
Proceedings of the 2003 international symposium on Physical design
Estimation of signal arrival times in the presence of delay noise
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient crosstalk noise modeling using aggressor and tree reductions
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Robust and passive model order reduction for circuits containing susceptance elements
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient model order reduction via multi-node moment matching
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Realizable parasitic reduction using generalized Y-Δ transformation
Proceedings of the 40th annual Design Automation Conference
Realizable RLCK circuit crunching
Proceedings of the 40th annual Design Automation Conference
Model order reduction of nonuniform transmission lines using integrated congruence transform
Proceedings of the 40th annual Design Automation Conference
NORM: compact model order reduction of weakly nonlinear systems
Proceedings of the 40th annual Design Automation Conference
Analog and RF circuit macromodels for system-level analysis
Proceedings of the 40th annual Design Automation Conference
Electrical Modeling of Integrated-Package Power and Ground Distributions
IEEE Design & Test
Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Improved model-order reduction by using spacial information in moments
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Poor Man's TBR: A Simple Model Reduction Scheme
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Passivity-preserving model reduction via a computationally efficient project-and-balance scheme
Proceedings of the 41st annual Design Automation Conference
A linear fractional transform (LFT) based model for interconnect parametric uncertainty
Proceedings of the 41st annual Design Automation Conference
Exploiting input information in a model reduction algorithm for massively coupled parasitic networks
Proceedings of the 41st annual Design Automation Conference
Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects
Proceedings of the 41st annual Design Automation Conference
Interconnect Macromodelling and Approximation of Matrix Exponent
Analog Integrated Circuits and Signal Processing
Analog Macromodeling using Kernel Methods
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A General S-Domain Hierarchical Network Reduction Algorithm
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Analytic Modeling of Interconnects for Deep Sub-Micron Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Piecewise quadratic waveform matching with successive chord iteration
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A mixed-mode extraction flow for high performance microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Parametric reduced order modeling for interconnect analysis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Realizable parasitic reduction for distributed interconnects using matrix pencil technique
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Noise Macromodel for Radio Frequency Integrated Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Model-Order Reduction Based on PRONY's Method
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Combined FDTD/Macromodel Simulation of Interconnected Digital Devices
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Fast interval-valued statistical interconnect modeling and reduction
Proceedings of the 2005 international symposium on Physical design
Proceedings of the 42nd annual Design Automation Conference
Scalable trajectory methods for on-demand analog macromodel extraction
Proceedings of the 42nd annual Design Automation Conference
Piece-wise approximations of RLCK circuit responses using moment matching
Proceedings of the 42nd annual Design Automation Conference
Structure preserving reduction of frequency-dependent interconnect
Proceedings of the 42nd annual Design Automation Conference
EFFICIENT THERMAL SIMULATION FOR RUN-TIME TEMPERATURE TRACKING AND MANAGEMENT
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Computation of signal threshold crossing times directly from higher order moments
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
True crosstalk aware incremental placement with noise map
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Variational interconnect analysis via PMTBR
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical crosstalk aggressor alignment aware interconnect delay calculation
Proceedings of the 2006 international workshop on System-level interconnect prediction
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
RCLK-VJ network reduction with Hurwitz polynomial approximation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A frequency separation macromodel for system-level simulation of RF circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Analysis of buffered hybrid structured clock networks
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A wideband hierarchical circuit reduction for massively coupled interconnects
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Comprehensive frequency dependent interconnect extraction and evaluation methodology
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2006 international symposium on Physical design
Efficient Model Update for General Link-Insertion Networks
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Compact Reduced Order Modeling for Multiple-Port Interconnects
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical gate delay calculation with crosstalk alignment consideration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Crosstalk analysis in nanometer technologies
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Parameterized model order reduction of nonlinear dynamical systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A more reliable reduction algorithm for behavioral model extraction
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An efficient method for terminal reduction of interconnect circuits considering delay variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Expanding the frequency range of AWE via time shifting
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function
Proceedings of the conference on Design, automation and test in Europe: Proceedings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Model order reduction of linear networks with massive ports via frequency-dependent port packing
Proceedings of the 43rd annual Design Automation Conference
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power
Proceedings of the 2006 international symposium on Low power electronics and design
Analog Integrated Circuits and Signal Processing
Empire: an efficient and compact multiple-parameterized model order reduction method
Proceedings of the 2007 international symposium on Physical design
Minimal skew clock embedding considering time variant temperature gradient
Proceedings of the 2007 international symposium on Physical design
VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial
Integration, the VLSI Journal
A fast block structure preserving model order reduction for inverse inductance circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Simultaneous power and thermal integrity driven via stapling in 3D ICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Faster, parametric trajectory-based macromodels via localized linear reductions
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Circuit-simulated obstacle-aware Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
WAVSTAN: waveform based variational static timing analysis
Proceedings of the conference on Design, automation and test in Europe
Fast positive-real balanced truncation of symmetric systems using cross Riccati equations
Proceedings of the conference on Design, automation and test in Europe
Random sampling of moment graph: a stochastic Krylov-reduction algorithm
Proceedings of the conference on Design, automation and test in Europe
SBPOR: second-order balanced truncation for passive order reduction of RLC circuits
Proceedings of the 44th annual Design Automation Conference
Parameterized macromodeling for analog system-level design exploration
Proceedings of the 44th annual Design Automation Conference
An efficient terminal and model order reduction algorithm
Integration, the VLSI Journal
Sparse and passive reduction of massively coupled large multiport interconnects
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A nonlinear cell macromodel for digital applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Compact modeling of variational waveforms
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Parameterized model order reduction via a two-directional Arnoldi process
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Hierarchical Krylov subspace reduced order modeling of large RLC circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Architecture-level thermal behavioral characterization for multi-core microprocessors
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
DeMOR: decentralized model order reduction of linear networks with massive ports
Proceedings of the 45th annual Design Automation Conference
Towards a more physical approach to gate modeling for timing, noise, and power
Proceedings of the 45th annual Design Automation Conference
ETBR: extended truncated balanced realization method for on-chip power grid network analysis
Proceedings of the conference on Design, automation and test in Europe
SPARE: a Scalable algorithm for passive, structure preserving, Parameter-Aware model order REduction
Proceedings of the conference on Design, automation and test in Europe
Model-order reductions for MIMO systems using global Krylov subspace methods
Mathematics and Computers in Simulation
Multiple block structure-preserving reduced order modeling of interconnect circuits
Integration, the VLSI Journal
Hierarchical Krylov subspace based reduction of large interconnects
Integration, the VLSI Journal
A two-directional Arnoldi process and its application to parametric model order reduction
Journal of Computational and Applied Mathematics
Guaranteed stable projection-based model reduction for indefinite and unstable linear systems
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Sparse implicit projection (SIP) for reduction of general many-terminal networks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Sparse and Passive Reduced-Order Interconnect Modeling by Eigenspace Method
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast variational interconnect delay and slew computation using quadratic models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Projection method for order reduction of analog circuits
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
ARMS - automatic residue-minimization based sampling for multi-point modeling techniques
Proceedings of the 46th Annual Design Automation Conference
GHM: a generalized Hamiltonian method for passivity test of impedance/admittance descriptor systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Numerical Simulation and Modelling of Electronic and Biochemical Systems
Foundations and Trends in Electronic Design Automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Architecture-level thermal characterization for multicore microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Passivity test of immittance descriptor systems based on generalized Hamiltonian methods
IEEE Transactions on Circuits and Systems II: Express Briefs
SPARE: a scalable algorithm for passive, structure preserving, parameter-aware model order reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
EMPIRE: an efficient and compact multiple-parameterized model-order reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate predictive interconnect modeling for system-level design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated compact dynamical modeling: an enabling tool for analog designers
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PABTEC: passivity-preserving balanced truncation for electrical circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
HORUS - high-dimensional model order reduction via low moment-matching upgraded sampling
Proceedings of the Conference on Design, Automation and Test in Europe
On passivity of the super node algorithm for EM modeling of interconnect systems
Proceedings of the Conference on Design, Automation and Test in Europe
Model order reduction for large LTI control systems
Journal of Computer and Systems Sciences International
On the efficient reduction of complete EM based parametric models
Proceedings of the Conference on Design, Automation and Test in Europe
Accurate direct and indirect on-chip temperature sensing for efficient dynamic thermal management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Passive rational interpolation-based reduction via Carathéodory extension for general systems
IEEE Transactions on Circuits and Systems II: Express Briefs
Efficient model reduction of interconnects via double gramians approximation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
An extension of the generalized Hamiltonian method to S-parameter descriptor systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fast analysis of a large-scale inductive interconnect by block-structure-preserved macromodeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Balanced truncation for time-delay systems via approximate Gramians
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A Framework for Reduced Order Modeling with Mixed Moment Matching and Peak Error Objectives
SIAM Journal on Scientific Computing
Implementation of a transmission line model with the PEEC method for lightning surge analysis
EE'11 Proceedings of the 6th IASME/WSEAS international conference on Energy & environment
Efficient simulation of nonuniform transmission lines using integrated congruence transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On dominant poles and model reduction of second order time-delay systems
Applied Numerical Mathematics
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Original article: Machine tool simulation based on reduced order FE models
Mathematics and Computers in Simulation
Efficient analytical macromodeling of large analog circuits by transfer function trajectories
Proceedings of the International Conference on Computer-Aided Design
Model order reduction of fully parameterized systems by recursive least square optimization
Proceedings of the International Conference on Computer-Aided Design
Modeling and design for beyond-the-die power integrity
Proceedings of the International Conference on Computer-Aided Design
3POr: parallel projection based parameterized order reduction for multi-dimensional linear models
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Model reduction for RF MEMS simulation
PARA'04 Proceedings of the 7th international conference on Applied Parallel Computing: state of the Art in Scientific Computing
Structure-preserving model reduction
PARA'04 Proceedings of the 7th international conference on Applied Parallel Computing: state of the Art in Scientific Computing
Receiver modeling for static functional crosstalk analysis
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 49th Annual Design Automation Conference
Structure preserving model-order reductions of MIMO second-order systems using Arnoldi methods
Mathematical and Computer Modelling: An International Journal
Model order reduction of coupled circuit-device systems
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
Fast timing analysis of clock networks considering environmental uncertainty
Integration, the VLSI Journal
Proceedings of the International Conference on Computer-Aided Design
Structure-preserving model reduction of passive and quasi-active neurons
Journal of Computational Neuroscience
ABCD-L: approximating continuous linear systems using boolean models
Proceedings of the 50th Annual Design Automation Conference
Decentralized and passive model order reduction of linear networks with massive ports
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parametric dominant pole algorithm for parametric model order reduction
Journal of Computational and Applied Mathematics
Mathematics and Computers in Simulation
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This paper describes an algorithm for generating provably passive reduced-order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to macromodel stability, macromodel passivity is needed to guarantee the overall circuit stability once the active and passive driver/load models are connected. The approach proposed here, PRIMA, is a general method for obtaining passive reduced-order macromodels for linear RLC systems. In this paper, PRIMA is demonstrated in terms of a simple implementation which extends the block Arnoldi technique to include guaranteed passivity while providing superior accuracy. While the same passivity extension is not possible for MPVL, comparable accuracy in the frequency domain for all examples is observed