Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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Statistical clock tree routing for robustness to process variations
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ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
TACO: temperature aware clock-tree optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
iTEM: a temperature-dependent electromigration reliability diagnosis tool
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temperature and supply Voltage aware performance and power modeling at microarchitecture level
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variations, margins, and statistics
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Thermal sensor allocation and placement for reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Buffered clock tree sizing for skew minimization under power and thermal budgets
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Novel binary linear programming for high performance clock mesh synthesis
Proceedings of the International Conference on Computer-Aided Design
Fast timing analysis of clock networks considering environmental uncertainty
Integration, the VLSI Journal
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty
Integration, the VLSI Journal
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The existing temperature-aware clock embedding assumes a time-invariant temperature gradient. However, it is not solved how to find the worst-case temperature gradient leading to the worst case skew. In this paper, we develop a PErturbation based Clock Optimization(PECO) considering the time-variant temperature gradient. For a given clock topology, we minimizethe worst case skew without asking for the worst case temperature map. We decide the merging point level by level based on the sensitivity of the skew with respect to the change of merging point. Such sensitivity is calculated using a parameterized model, which is compressed by a singular-value-decomposition (SVD) and K-meansbased clustering considering the temperature correlation. The experimental results show that our algorithm reduces worst-case skew by up to 5X compared to the existing zero skew based ZST/DME method with small (up to 1%) wirelength overhead.