Interconnect thermal modeling for determining design limits on current density
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Proceedings of the 2001 international symposium on Physical design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Clock Distribution Network Optimization under Self-Heating and Timing Constraints
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
An electromigration and thermal model of power wires for a priori high-level reliability prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power
Proceedings of the 2006 international symposium on Low power electronics and design
Minimal skew clock embedding considering time variant temperature gradient
Proceedings of the 2007 international symposium on Physical design
Efficient computation of current flow in signal wires for reliability analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Electro-thermal analysis of multi-fin devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-chip em-sensitive interconnect structures
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty
Integration, the VLSI Journal
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In this paper, we present a new electromigration reliability diagnosis tool (iTEM) for CMOS VLSI circuits. Unlike previous electromigration reliability tools, iTEM can estimate the interconnect temperature rise due to joule heating and heat conduction from the substrate using a newly developed lumped thermal model. By including the temperature effect, iTEM provides much more accurate electromigration reliability diagnosis. Moreover, it is computationally efficient, and can analyze circuit layouts containing tens of thousands of transistors on a desktop workstation