On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
iTEM: a temperature-dependent electromigration reliability diagnosis tool
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
Thermal aware cell-based full-chip electromigration reliability analysis
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Efficient full-chip thermal modeling and analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Temperature-aware routing in 3D ICs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Integrating dynamic thermal via planning with 3D floorplanning algorithm
Proceedings of the 2006 international symposium on Physical design
METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Thermal via planning for 3-D ICs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On-chip bus thermal analysis and optimization
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Proceedings of the 43rd annual Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
An analysis of timing violations due to spatially distributed thermal effects in global wires
Proceedings of the 44th annual Design Automation Conference
Electro-thermal analysis of multi-fin devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation study
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
An accurate interconnect thermal model using equivalent transmission line circuit
Proceedings of the Conference on Design, Automation and Test in Europe
A new technique of multi-layer thermal analysis for VLSI chips
MMACTEE'07 Proceedings of the 9th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
New adaptive encoding schemes for switching activity balancing in on-chip buses
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Electrothermal analysis of spin-transfer-torque random access memory arrays
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special issue on memory technologies
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This paper presents both compact analytical models and fast SPICE based 3-D electro-thermal simulation methodology to characterize thermal effects due to Joule heating in high performance Cu/low-k interconnects under steady-state and transient stress conditions. The results demonstrate excellent agreement with experimental data and those using Finite Element (FE) thermal simulations (ANSYS). The effect of vias, as additional heat sinking paths to alleviate the temp erature rise in the metal wires, is included in our analysis to provide more accurate and realistic thermal diagnosis. It shows that the effectiveness of vias in reducing the temperature rise in interconnects is highly dependent on the via separation and the dielectric materials used. The analytical model is then applied to estimate the temperature distribution in multi-level interconnects. In addition, we discuss the possibility that, under the impact of thermal effects, the performance improvement expected from the use of low-k dielectric materials may be degraded. Furthermore, thermal coupling between wires is evaluated and found to be significant. Finally, the impact of metal wire aspect ratio on interconnect thermal characteristics is discussed.