On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An analysis of timing violations due to spatially distributed thermal effects in global wires
Proceedings of the 44th annual Design Automation Conference
Interconnect thermal modeling for accurate simulation of circuit timing and reliability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Thermal-aware bus-driven floorplanning
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Bus-driven floorplanning with thermal consideration
Integration, the VLSI Journal
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This paper presents an accurate interconnect thermal model for analyzing the temperature distribution of an on-chip interconnect wire. The model addresses the ambient temperatures and the heat transfer rates of the packaging materials. Particularly, the model considers the effect of the interconnect temperature gradients. The paper employs an equivalent transmission line circuit to obtain the temperature distribution solution from the model. Then an O (n) algorithm is introduced to compute the interconnect temperatures. Experimental results demonstrate the accuracy of the thermal model, by comparisons with the computational fluid dynamics tool FLUENT.