Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Analysis and optimization of thermal issues in high-performance VLSI
Proceedings of the 2001 international symposium on Physical design
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs
Proceedings of the 2002 international symposium on Physical design
3D thermal-ADI: an efficient chip-level transient thermal simulator
Proceedings of the 2003 international symposium on Physical design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
Multi-bend bus driven floorplanning
Proceedings of the 2005 international symposium on Physical design
On-chip bus thermal analysis and optimization
Proceedings of the conference on Design, automation and test in Europe: Proceedings
OPC-Friendly Bus Driven Floorplanning
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
TCG-based multi-bend bus driven floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Bus-aware microarchitectural floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Thermal-driven analog placement considering device matching
Proceedings of the 46th Annual Design Automation Conference
Bus via reduction based on floorplan revising
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Bus-pin-aware bus-driven floorplanning
Proceedings of the 20th symposium on Great lakes symposium on VLSI
An accurate interconnect thermal model using equivalent transmission line circuit
Proceedings of the Conference on Design, Automation and Test in Europe
Thermal signature: a simple yet accurate thermal index for floorplan optimization
Proceedings of the 48th Design Automation Conference
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
As the number of buses in multi-core SoC designs increase, bus planning problems become a dominant factor in determining the chip performance. To cope with these issues, it is desirable to consider them in the early floorplanning stage. Recently, many bus-driven floorplanners have been proposed in the literature. However, those proposed algorithms only consider the bus planning problem without the thermal effect. As a result, there are hotspots which result in high chip temperature on the chip. In this paper, a thermal-aware bus-driven floorplanning algorithm is proposed to separate hotspots during the perturbation stage and to keep buses away from hotspots during the routing stage. To avoid time-consuming thermal simulations, the superposition of thermal profiles which are the thermal distribution of each module is adopted to efficiently estimate the module temperature. Compared with the state-of-the-art bus-driven floorplanner, experimental results demonstrate that the proposed algorithm can effectively separate hotspots and reduce the chip temperature.