FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Floorplanning with abutment constraints and L-shpaed/T-shaped blocks baed on corner block list
Proceedings of the 38th annual Design Automation Conference
Floorplanning with alignment and performance constraints
Proceedings of the 39th annual Design Automation Conference
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Semi-detailed bus routing with variation reduction
Proceedings of the 2007 international symposium on Physical design
A simultaneous bus orientation and bused pin flipping algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
TCG-based multi-bend bus driven floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Bus-aware microarchitectural floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A new physical routing approach for robust bundled signaling on NoC links
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Bus via reduction based on floorplan revising
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Bus-pin-aware bus-driven floorplanning
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Thermal-aware bus-driven floorplanning
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Multi-bend bus-driven floorplanning considering fixed-outline constraints
Integration, the VLSI Journal
| Hi-index | 0.00 |
In this paper, the problem of bus-driven floorplanning is addressed. Given a set of blocks and the bus specification (the width of each bus and the blocks that the bus need to go through), we will generate a floorplan solution such that all the buses go through its blocks, with the area of the floorplan and the total area of the buses minimized. The approach proposed is based on a Simulated Annealing framework. Using the sequence pair representation, we derived the necessary conditions for feasible buses, for which we allow 0-bend, one-bend, or two-bend. Then, we will check whether there are buses that cannot be placed at the same time. Finally, a solution will be generated giving the coordinates of the modules and the buses. Comparing with the results of the algorithm by Xiang et al., the dead space of the floorplan obtained is reduced. Besides, our algorithm can handle buses going through many blocks. For example, if the buses have to go through more than 10 blocks, is not able to generate any solution while our algorithm can still generate solutions of good quality.