Fast evaluation of sequence pair in block placement by longest common subsequence computation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
FAST-SP: a fast algorithm for block placement based on sequence pair
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs
Proceedings of the 2002 international symposium on Physical design
Floorplanning with alignment and performance constraints
Proceedings of the 39th annual Design Automation Conference
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
Multi-bend bus driven floorplanning
Proceedings of the 2005 international symposium on Physical design
Physical design implementation of segmented buses to reduce communication energy
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Optimal redistribution of white space for wire length minimization
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Semi-detailed bus routing with variation reduction
Proceedings of the 2007 international symposium on Physical design
Multi-bend bus driven floorplanning
Integration, the VLSI Journal
A simultaneous bus orientation and bused pin flipping algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
TCG-based multi-bend bus driven floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A new physical routing approach for robust bundled signaling on NoC links
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Bus via reduction based on floorplan revising
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Bus-pin-aware bus-driven floorplanning
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Thermal-aware bus-driven floorplanning
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Bus-driven floorplanning with bus pin assignment and deviation minimization
Integration, the VLSI Journal
Multi-bend bus-driven floorplanning considering fixed-outline constraints
Integration, the VLSI Journal
Statistical thermal modeling and optimization considering leakage power variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we present an integrated approach to floorplanningand bus planning, i.e., bus-driven floorplanning (BDF). We are givena set of circuit blocks and the bus specifications (i.e., the net list ofblocks for the buses). A feasible BDF solution is a placement ofall circuit blocks such that each bus can be realized as a rectangularstrip (horizontal or vertical) going through all the blocks connectedby the bus. The objective is to determine a feasible BDF solutionthat minimizes floorplan area and total bus area. Our approachis based upon the sequence-pair floorplan representation. After acareful analysis of the relationship between bus ordering and blockordering in the floorplan represented by a sequence pair, we derivefeasibility conditions on sequence pairs that give feasible BDFsolutions. Experimental results demonstrate the efficiency and effectivenessof our algorithm.