Bus via reduction based on floorplan revising

Authors:
Ou He;Sheqin Dong;Jinian Bian;Sotoshi Goto;Chung-Kuan Cheng
Affiliations:
Tsinghua University, Beijing, China;Tsinghua University, Beijing, China;Tsinghua University, Beijing, China;Waseda University, Kitakyushu, Japan;University of California, San Diego, San Diego, CA, USA
Venue:
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Year:
2010

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Abstract

As a global interconnection, bus is critical for chip performance in deep submicron technology. Reducing bus routing vias will facilitate the lithography and give bus routing a higher yield and also a higher performance. In this paper, we present a floorplan revising method to minimize the number of reducible routing vias with a controllable loss on the chip area and wirelength. Therefore, it is easy to make a proper tradeoff between via reduction and revising loss. Experiments show that our method reaches a 96.2% and 93.5% reduction of routing vias, which is close to 100% and runs fast. Besides, our revising is friendly to all third-party floorplanners, which can be applied to any existing floorplans to reduce vias. It is also scalable to larger benchmarks.