Bus via reduction based on floorplan revising
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Thermal-aware bus-driven floorplanning
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Bus-driven floorplanning with bus pin assignment and deviation minimization
Integration, the VLSI Journal
Bus-driven floorplanning with thermal consideration
Integration, the VLSI Journal
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In this paper, we address the interconnect-driven floorplanning problem that integrates OPC-friendly bus assignment with floorplanning. Buses consist of a number of horizontal/vertical wires with identical widths. The positions of buses must be carefully designed so that the related blocks can connect to the buses with short connections. Meanwhile, as technologies march into deep sub-micron, sub-wavelength lithography causes many issues in lithographic processes. Off axis illumination (OAI) brings up the forbidden pitch issue, which could lower the yield substantially. In this paper, we first propose a litho model so that the optimal pitch can be efficiently computed for each bus. Then we present an exact algorithm to find the optimal position of a bus such that the total length of bus connections, i.e., connections from block centers to the buses, is minimized. The running time is O(k lnk) where k is the number of blocks that the bus connects. Next, we propose a linear programming based algorithm to exactly resolve overlaps among buses as well as minimizing bus connections. Furthermore, a fast heuristic approach is presented to speed up the overlap removal process. The bus assignment algorithms are smoothly integrated into the simulated annealing process of floorplanning to produce a compact floorplan with OPC-friendly buses. This work is the first one to consider litho impacts during the early floorplanning stage.