Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Introduction to algorithms
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs
Proceedings of the 2002 international symposium on Physical design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Modern floorplanning based on fast simulated annealing
Proceedings of the 2005 international symposium on Physical design
Semi-detailed bus routing with variation reduction
Proceedings of the 2007 international symposium on Physical design
OPC-Friendly Bus Driven Floorplanning
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Multi-bend bus driven floorplanning
Integration, the VLSI Journal
A simultaneous bus orientation and bused pin flipping algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
TCG-based multi-bend bus driven floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Bus-aware microarchitectural floorplanning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Bus via reduction based on floorplan revising
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Bus-pin-aware bus-driven floorplanning
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Bus-driven floorplanning with thermal consideration
Integration, the VLSI Journal
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As the number of buses increase substantially in multi-core SoC designs, the bus planning problem has become the dominant factor in determining the performance and power consumption of SoC designs. To cope with the bus planning problem, it is desirable to consider this issue in early floorplanning stage. Recently, the bus-driven floorplanning problem has attracted much attention in the literature. However, current algorithms adopt an over-simplified formulation which ignores the orientation of the bus pin, the chip performance may be deteriorated. In this paper, we propose the bus-driven floorplanning algorithm that fully considers the impact of the bus pin. By fully utilizing the position and orientation of the bus pin, bus bendings are not restricted to occur at the module of the same bus, then more flexible bus shape is obtained. With more flexibility on the bus shape, the size of the solution space is increased and a better bus-driven floorplanning solution can be obtained. In conference version, compared with the bus-driven floorplanner [6], experimental results show that our algorithm performs better in runtime by 3.5x, bus wirelength by 1.4x, and deadspace by 1.2x, respectively. In this paper, we improve the algorithm in [11] to obtain better driver-load delay variation among all bus bits.