Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs
Proceedings of the 2002 international symposium on Physical design
CAD computation for manufacturability: can we save VLSI technology from itself?
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Topological routing of multi-bit data buses
DAC '84 Proceedings of the 21st Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi-bend bus driven floorplanning
Proceedings of the 2005 international symposium on Physical design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simultaneous bus orientation and bused pin flipping algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A new physical routing approach for robust bundled signaling on NoC links
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Bus-pin-aware bus-driven floorplanning
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Bus-driven floorplanning with bus pin assignment and deviation minimization
Integration, the VLSI Journal
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A bus routing algorithm is presented which not only minimizes wire length but also selects the bits in the bus to avoid twisting and conflicts. The resulting bus routes are regular, thus having strong immunity to variations. Minimization for wire length/delay differences between different bits is also implemented.