Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Routing tree construction under fixed buffer locations
Proceedings of the 37th Annual Design Automation Conference
The rectilinear Steiner arborescence problem is NP-complete
SODA '00 Proceedings of the eleventh annual ACM-SIAM symposium on Discrete algorithms
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Computing the Shortest Network under a Fixed Topology
IEEE Transactions on Computers
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Two hybrid evolutionary algorithms for the rectilinear Steiner arborescence problem
Proceedings of the 2004 ACM symposium on Applied computing
Average-case complexity of single-source shortest-paths algorithms: lower and upper bounds
Journal of Algorithms - Special issue: Twelfth annual ACM-SIAM symposium on discrete algorithms
Layer assignment for reliable system-on-package
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A tree-based genetic algorithm for building rectilinear Steiner arborescences
Proceedings of the 8th annual conference on Genetic and evolutionary computation
Timing-driven Steiner trees are (practically) free
Proceedings of the 43rd annual Design Automation Conference
Semi-detailed bus routing with variation reduction
Proceedings of the 2007 international symposium on Physical design
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Proceedings of the 46th Annual Design Automation Conference
Physical synthesis of bus matrix for high bandwidth low power on-chip communications
Proceedings of the 19th international symposium on Physical design
A tree-based topology synthesis for on-chip network
Proceedings of the International Conference on Computer-Aided Design
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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Given an undirected graph G=(V, E) with positive edge weights (lengths) ω: E→ℜ+, a set of terminals (sinks) N⊆V, and a unique root node eεN, a shortest path Steiner arborescence (hereafter an arborescence) is a Steiner tree rooted at, spanning all terminals in N such that every source-to-sink path is a shortest path in G. Given a triple (G, N, r), the minimum shortest path Steiner arborescence (MSPSA) problem seeks an arborescence with minimum weight. The MSPSA problem has various applications in the areas of physical design of very large-scale integrated circuits (VLSI), multicast network communication, and supercomputer message routing; various eases have been studied in the literature. In this paper, we propose several heuristics and exact algorithms for the MSPSA problem with applications to VLSI physical design. Experiments indicate that our heuristics generate near optimal results and achieve speedups of orders of magnitude over existing algorithms