The triptych FPGA architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Introduction to VLSI Systems
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy
ARVLSI '01 Proceedings of the 2001 Conference on Advanced Research in VLSI
Design of programmable interconnect for sublithographic programmable logic arrays
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Logic block clustering of large designs for channel-width constrained FPGAs
Proceedings of the 42nd annual Design Automation Conference
Neuromorphic architectures for nanoelectronic circuits: Research Articles
International Journal of Circuit Theory and Applications - Nanoelectric Circuits
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
CMOL crossnets as pattern classifiers
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Towards Nanoelectronics Processor Architectures
Journal of Electronic Testing: Theory and Applications
CMOL: Second life for silicon?
Microelectronics Journal
The amorphous FPGA architecture
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Design and defect tolerance beyond CMOS
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Towards a framework for designing applications onto hybrid nano/CMOS fabrics
Microelectronics Journal
Hybrid nanoelectronics: future of computer technology
Journal of Computer Science and Technology
Online multiple error detection in crossbar nano-architectures
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Routing congestion removing of CMOL FPGA circuits by a recursive method
MINO'10 Proceedings of the 9th WSEAS international conference on Microelectronics, nanoelectronics, optoelectronics
Monolithically stackable hybrid FPGA
Proceedings of the Conference on Design, Automation and Test in Europe
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Online detection of multiple faults in crossbar nano-architectures using dual rail implementations
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
A Reconfigurable PLA Architecture for Nanomagnet Logic
ACM Journal on Emerging Technologies in Computing Systems (JETC)
NanoCMOS-molecular realization of rijndael
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Efficient CMOL nanoscale hybrid circuit cell assignment using simulated evolution heuristic
Proceedings of the great lakes symposium on VLSI
Cell assignment in hybrid CMOS/nanodevices architecture using Tabu Search
Applied Intelligence
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This report describes a preliminary evaluation of performance of a cell-FPGA-like architecture for future hybrid "CMOL" circuits. Such circuits will combine a semiconduc-tor-transistor (CMOS) stack and a two-level nanowire crossbar with molecular-scale two-terminal nanodevices (program-mable diodes) formed at each crosspoint. Our cell-based architecture is based on a uniform CMOL fabric of "tiles". Each tile consists of 12 four-transistor basic cells and one (four times larger) latch cell. Due to high density of nanodevices, which may be used for both logic and routing functions, CMOL FPGA may be reconfigured around defective nanodevices to provide high defect tolerance. Using a semi-custom set of design automation tools we have evaluated CMOL FPGA performance for the Toronto 20 benchmark set, so far without optimization of several parameters including the power supply voltage and nanowire pitch. The results show that even without such optimization, CMOL FPGA circuits may provide a density advantage of more than two orders of magnitude over the traditional CMOS FPGA with the same CMOS design rules, at comparable time delay, acceptable power consumption and potentially high defect tolerance.