Strongly Fault Secure PLAs and Totally Self-Checking Checkers
IEEE Transactions on Computers
PLATYPUS: a PLA test pattern generation tool
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
PLA based synthesis and testing of hazard free logic
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Application-independent defect-tolerant crossbar nano-architectures
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays
DSN '07 Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs
Proceedings of the conference on Design, automation and test in Europe
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
Multiple Fault Detection in Programmable Logic Arrays
IEEE Transactions on Computers
Selective Hardening of NanoPLA Circuits
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
CMOS/nano co-design for crossbar-based molecular electronic systems
IEEE Transactions on Nanotechnology
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Crossbar nano-architectures based on self-assembled nano-structures are promising alternatives for current CMOS technology, which is facing serious challenges for further down-scaling. One of the major challenges in this nanotechnology is elevated failure rate due to atomic device sizes and inherent lack of control in self-assembly fabrication. Therefore, high permanent and transient failure rates lead to multiple faults during lifetime operation of crossbar nano architectures. In this paper, we present a concurrent multiple error detection scheme for multistage crossbar nano-architectures based on dual-rail implementations of logic functions. We prove the detectability of all single faults as well as most classes of multiple faults in this scheme. Based on statistical multiple fault injection, we compare the proposed technique with other online error detection and masking techniques such as Triple Module Redundancy (TMR), duplication, and parity checking, in terms of fault coverage as well as area and delay overhead.