IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Designing CMOS/molecular memories while considering device parameter variations
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
MBARC: a scalable memory based reconfigurable computing framework for nanoscale devices
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Logic synthesis with nanowire crossbar: reality check and standard cell-based integration
Proceedings of the conference on Design, automation and test in Europe
A study of asynchronous design methodology for robust CMOS-nano hybrid system design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Nanowire crossbar logic and standard cell-based integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Online multiple error detection in crossbar nano-architectures
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Variation tolerant logic mapping for crossbar array nano architectures
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Online detection of multiple faults in crossbar nano-architectures using dual rail implementations
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Computing with nanoscale memory: Model and architecture
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
NanoCMOS-molecular realization of rijndael
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Design trade-offs for high density cross-point resistive memory
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Design investigation of nanoelectronic circuits using crossbar-based nanoarchitectures
Microelectronics Journal
Design exploration of hybrid CMOS and memristor circuit by new modified nodal analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Future electronic systems will need to adopt novel nanoelectronic solutions to keep pace with Moore's Law. Crossbar-based molecular electronics are among the most promising of nanotechnologies. However, circuits similar to the conventional mainstream electronics of today will have a presence in future complex systems for some time. This paper presents a circuit paradigm where silicon and molecular electronics are integrated. We discuss methods for realizing memory and logic using nanoscale crossbars as well as for interfacing the crossbars to CMOS circuitry. Using custom nanoscale device models, we perform circuit simulation and analysis of the crossbar circuits and the peripheral CMOS circuitry. Finally, we present a design methodology to accompany the CMOS/nano paradigm.