NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Algorithms for VLSI Design Automation
Algorithms for VLSI Design Automation
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Application-independent defect tolerance of reconfigurable nanoarchitectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Future Trends in Microelectronics: Up the Nano Creek
Future Trends in Microelectronics: Up the Nano Creek
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
CMOS/nano co-design for crossbar-based molecular electronic systems
IEEE Transactions on Nanotechnology
Variation-aware logic mapping for crossbar nano-architectures
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Reliable logic mapping on Nano-PLA architectures
Proceedings of the great lakes symposium on VLSI
ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Bottom-up self-assembly nanofabrication process yields nanodevices with significantly more variations compared to the conventional top-down lithography used in CMOS fabrication. This is in addition to an increased defect density expected for self-assembled nanodevices. Therefore, it is one of the major design challenges to tolerate variation, in addition to defect tolerance, in emerging nano architectures. In this paper, we present a solution for variation tolerant logic mapping for FET based crossbar array nano architectures using Simulated Annealing. Furthermore, we extended the framework for defect tolerance. Experimental results including comparison with exact method confirm the effectiveness of the proposed approach.