Computer
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Opportunities and challenges in application-tuned circuits and architectures based on nanodevices
Proceedings of the 1st conference on Computing frontiers
Defect tolerant probabilistic design paradigm for nanotechnologies
Proceedings of the 41st annual Design Automation Conference
A Probabilistic-Based Design Methodology for Nanoscale Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Design of programmable interconnect for sublithographic programmable logic arrays
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Large-signal two-terminal device model for nanoelectronic circuit analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Proceedings of the 42nd annual Design Automation Conference
Analysis of a Mask-Based Nanowire Decoder
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies
IEEE Design & Test
Evaluation of design strategies for stochastically assembled nanoarray memories
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
NANA: A nano-scale active network architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A nano-scale reconfigurable mesh with spin waves
Proceedings of the 3rd conference on Computing frontiers
The impact of the nanoscale on computing systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Nanocomputing in the presence of defects and faults: a survey
Nano, quantum and molecular computing
Defect tolerance at the end of the roadmap
Nano, quantum and molecular computing
A probabilistic-based design for nanoscale computation
Nano, quantum and molecular computing
Law of large numbers system design
Nano, quantum and molecular computing
Origins and motivations for design rules in QCA
Nano, quantum and molecular computing
Topology aware mapping of logic functions onto nanowire-based crossbar architectures
Proceedings of the 43rd annual Design Automation Conference
Radial addressing of nanowires
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Application-independent defect tolerance of reconfigurable nanoarchitectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Automated design flow for diode-based nanofabrics
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Application-independent defect-tolerant crossbar nano-architectures
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Journal of Electronic Testing: Theory and Applications
Defect-tolerant Logic with Nanoscale Crossbar Circuits
Journal of Electronic Testing: Theory and Applications
Towards Nanoelectronics Processor Architectures
Journal of Electronic Testing: Theory and Applications
The spin-wave nanoscale reconfigurable mesh and the labeling problem
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A self-organizing defect tolerant SIMD architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Interactive presentation: Improving the fault tolerance of nanometric PLA designs
Proceedings of the conference on Design, automation and test in Europe
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs
Proceedings of the conference on Design, automation and test in Europe
Towards an ultra-low-power architecture using single-electron tunneling transistors
Proceedings of the 44th annual Design Automation Conference
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Microelectronic Engineering
A low-power reconfigurable logic array based on double-gate transistors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Towards a holistic CAD platform for nanotechnologies
Microelectronics Journal
Cost-driven repair optimization of reconfigurable nanowire crossbar systems with clustered defects
Journal of Systems Architecture: the EUROMICRO Journal
An efficient test and characterization approach for nanowire-based architectures
Proceedings of the 21st annual symposium on Integrated circuits and system design
Nanowire addressing with randomized-contact decoders
Theoretical Computer Science
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
BISM: built-in self map for hybrid crossbar nano-architectures
Proceedings of the 19th ACM Great Lakes symposium on VLSI
The effects of logic partitioning in a majority logic based CMOS-NANO FPGA
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Low-overhead defect tolerance in crossbar nanoarchitectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Hybrid nanoelectronics: future of computer technology
Journal of Computer Science and Technology
A study of asynchronous design methodology for robust CMOS-nano hybrid system design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
An outlook on design technologies for future integrated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nanowire crossbar logic and standard cell-based integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Online multiple error detection in crossbar nano-architectures
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
NanoV: nanowire-based VLSI design
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Gate-level redundancy: a new design-for reliability paradigm for nanotechnologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Variation tolerant logic mapping for crossbar array nano architectures
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Online detection of multiple faults in crossbar nano-architectures using dual rail implementations
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Computing with nanoscale memory: Model and architecture
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
A fault-tolerant interconnect mechanism for NMR nanoarchitectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterization of single-electron tunneling transistors for designing low-power embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Defect-Aware Nanocrossbar Logic Mapping through Matrix Canonization Using Two-Dimensional Radix Sort
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Ultra-fine grain FPGAs: A granularity study
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Learning with memristive devices: How should we model their behavior?
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
Design Considerations for Multilevel CMOS/Nano Memristive Memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the International Conference on Computer-Aided Design
3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Fault-tolerant programmable logic array for nanoelectronics
International Journal of Circuit Theory and Applications
Design investigation of nanoelectronic circuits using crossbar-based nanoarchitectures
Microelectronics Journal
Defect-tolerant logic hardening for crossbar-based nanosystems
Proceedings of the Conference on Design, Automation and Test in Europe
ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Memristor-based combinational circuits: A design methodology for encoders/decoders
Microelectronics Journal
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Advances in our basic scientific understanding at the molecular and atomic level place us on the verge of engineering designer structures with key features at the single nanometer scale. This offers us the opportunity to design computing systems at what may be the ultimate limits on device size. At this scale, we are faced with new challenges and a new cost structure which motivates different computing architectures than we found efficient and appropriate in conventional very large scale integration (VLSI). We sketch a basic architecture for nanoscale electronics based on carbon nanotubes, silicon nanowires, and nano-scale FETs. This architecture can provide universal logic functionality with all logic and signal restoration operating at the nanoscale. The key properties of this architecture are its minimalism, defect tolerance, and compatibility with emerging bottom-up nanoscale fabrication techniques. The architecture further supports micro-to-nanoscale interfacing for communication with conventional integrated circuits and bootstrap loading.