NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Crossbar demultiplexers for nanoelectronics based on n-hot codes
IEEE Transactions on Nanotechnology
Defects and faults in QCA-based PLAs
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A hybrid nano-CMOS architecture for defect and fault tolerance
ACM Journal on Emerging Technologies in Computing Systems (JETC)
NanoV: nanowire-based VLSI design
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability
Proceedings of the Conference on Design, Automation and Test in Europe
Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Proceedings of the International Conference on Computer-Aided Design
Defect-tolerant logic hardening for crossbar-based nanosystems
Proceedings of the Conference on Design, Automation and Test in Europe
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Highly regular, nanodevice based architectures have been proposed to replace pure CMOS based architectures in the emerging post CMOS era. Since bottom-up self-assembly is used to build these architectures, regular nanowire crossbars are emerging as a promising candidate. While these regular structures resemble CMOS programmable logic arrays (PLAs), PLA logic synthesis methodologies fail to solve the associated problems since the length and connectivity constraints imposed by individual nanowires in these crossbars translate into challenges hitherto not considered. These strict topological constraints should be considered while mapping Boolean functions onto nanowire crossbars during logic synthesis. We develop a mathematical model for this problem, an algorithm to solve it and three heuristics to improve the algorithm runtime.