Topology aware mapping of logic functions onto nanowire-based crossbar architectures
Proceedings of the 43rd annual Design Automation Conference
Towards Nanoelectronics Processor Architectures
Journal of Electronic Testing: Theory and Applications
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs
Proceedings of the conference on Design, automation and test in Europe
Nanowire addressing with randomized-contact decoders
Theoretical Computer Science
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Demultiplexers are expected to be key components in interfacing submicrometer-scale and nano-scale electronic circuits. Designing them is challenging because most nanoarchitectures are limited to simple regular structures, such as crossbars, and nanoelectronic circuits in general are likely to be plagued with relatively high hard-defect and soft-error rates. Previous work has shown how linear codes can be used to design defect-tolerant demultiplexers using resistor or diode crossbars. We extend those results with nonlinear codes, constructing resistor and diode crossbar-based demultiplexers that have better electrical characteristics and defect tolerance for a given area of the nano substrate, at the cost of more complex address encoding circuitry.