Analysis of a Mask-Based Nanowire Decoder
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Probability and Computing: Randomized Algorithms and Probabilistic Analysis
Probability and Computing: Randomized Algorithms and Probabilistic Analysis
Evaluation of design strategies for stochastically assembled nanoarray memories
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Nanowire Addressing in the Face of Uncertainty
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Radial addressing of nanowires
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Address generation for nanowire decoders
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Nanowire addressing with randomized-contact decoders
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analysis of Mask-Based Nanowire Decoders
IEEE Transactions on Computers
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
Nonphotolithographic nanoscale memory density prospects
IEEE Transactions on Nanotechnology
Crossbar demultiplexers for nanoelectronics based on n-hot codes
IEEE Transactions on Nanotechnology
Deterministic addressing of nanoscale devices assembled at sublithographic pitches
IEEE Transactions on Nanotechnology
Assembling nanoscale circuits with randomized connections
IEEE Transactions on Nanotechnology
Demultiplexers for Nanoelectronics Constructed From Nonlinear Tunneling Resistors
IEEE Transactions on Nanotechnology
Stochastic nanoscale addressing for logic
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
| Hi-index | 5.23 |
Methods for assembling crossbars from nanowires (NWs) have been designed and implemented and methods for controlling individual NWs within a crossbar have also been proposed. However, implementation remains a challenge. A NW decoder is a device that controls many NWs with a much smaller number of lithographically produced mesoscale wires (MWs). Unlike traditional demultiplexers, all proposed NW decoders are assembled stochastically. In a randomized-contact decoder (RCD), for example, field-effect transistors are randomly created at about half of the NW/MW junctions. In this paper, we tightly bound the number of MWs required to produce a correctly functioning RCD with high probability. We show that the number of MWs is logarithmic in the number of NWs, even when manufacturing errors occur. We also analyze the overhead associated with controlling a stochastically assembled decoder. As we explain, lithographically-produced control circuitry must store information regarding which MWs control which NWs. This requires more area than the MWs themselves, but has received little attention elsewhere. Finally we analyze several simple testing algorithms for configuring this control circuitry. We demonstrate an unexpected tradeoff between testing time and the number of MWs required by an RCD.