The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Analysis of a Mask-Based Nanowire Decoder
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Evaluation of design strategies for stochastically assembled nanoarray memories
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
Nonphotolithographic nanoscale memory density prospects
IEEE Transactions on Nanotechnology
Nanowire addressing with randomized-contact decoders
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Nanowire addressing with randomized-contact decoders
Theoretical Computer Science
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Complete nanowire crossbar framework optimized for the multi-spacer patterning technique
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Decoding nanowire arrays fabricated with the multi-spacer patterning technique
Proceedings of the 46th Annual Design Automation Conference
An outlook on design technologies for future integrated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nanowire crossbar logic and standard cell-based integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stochastic nanoscale addressing for logic
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Hi-index | 0.00 |
We introduce radial encoding of nanowires (NWs), a new method of differentiating and controlling NWs by a small set of mesoscale wires for use in crossbar memories. We describe methods of controlling these NWs and give efficient manufacturing algorithms. These new encoding and decoding methods do not suffer from the misalignment characteristic of flow-aligned NWs. They achieve comparable effective pitch and resulting memory density with axially encoded NWs, while avoiding potential cases of address ambiguity and simplifying NW preparation. We also explore hybrid axial/radial encodings and show that they offer no net benefit over pure codes.