Evaluation of design strategies for stochastically assembled nanoarray memories
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Radial addressing of nanowires
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Designing CMOS/molecular memories while considering device parameter variations
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Nanowire addressing with randomized-contact decoders
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Defect-tolerant Logic with Nanoscale Crossbar Circuits
Journal of Electronic Testing: Theory and Applications
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
SCT: A novel approach for testing and configuring nanoscale devices
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Logic synthesis with nanowire crossbar: reality check and standard cell-based integration
Proceedings of the conference on Design, automation and test in Europe
Nanowire addressing with randomized-contact decoders
Theoretical Computer Science
Fault tolerant nano-memory with fault secure encoder and decoder
Proceedings of the 2nd international conference on Nano-Networks
Nanowire crossbar logic and standard cell-based integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Fault secure encoder and decoder for nanomemory applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid Redundancy for Defect Tolerance in Molecular Crossbar Memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design investigation of nanoelectronic circuits using crossbar-based nanoarchitectures
Microelectronics Journal
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Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 1011 b/cm2 with modest active power requirements under 0.6 W/Tb/s for random read operations.