Efficient Hardware Hashing Functions for High Performance Computers
IEEE Transactions on Computers
Space/time trade-offs in hash coding with allowable errors
Communications of the ACM
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Compressed Bit Fail Maps for Memory Fail Pattern Classification
Journal of Electronic Testing: Theory and Applications
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Fast Error-Correcting Circuits for Fault-Tolerant Memory
MTDT '04 Proceedings of the Records of the 2004 International Workshop on Memory Technology, Design and Testing
Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics
IEEE Design & Test
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A parallel Viterbi decoder for block cyclic and convolution codes
Signal Processing
Scalable defect mapping and configuration of memory-based nanofabrics
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
CMOS/nano co-design for crossbar-based molecular electronic systems
IEEE Transactions on Nanotechnology
Nonphotolithographic nanoscale memory density prospects
IEEE Transactions on Nanotechnology
History index of correct computation for fault-tolerant nano-computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a usable nanoscale memory system poses a significant challenge. In particular, we need to bootstrap a sea of unreliable bits into contiguous address ranges which are preferably as large as 4K-byte virtual memory pages. We accomplish this bootstrapping through a combination of dynamic error correction codes within 32-bit blocks and a static defect map which tracks usability of these blocks. The key insight is that statically-determined defect locations can be much more powerful than dynamically correcting for unknown locations, but that defect maps are only practical at a coarse granularity. Using a combination of BCH error correction codes and a Bloom-Filter-based defect map, we achieve a memory efficiency of 60% and 13% for 4K-byte pages at 1% and 10% bit-error rates, respectively.