NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Stochastic assembly of sublithographic nanoscale interfaces
IEEE Transactions on Nanotechnology
Application-independent defect tolerance of reconfigurable nanoarchitectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Application-independent defect-tolerant crossbar nano-architectures
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
On the use of Bloom filters for defect maps in nanocomputing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
MBARC: a scalable memory based reconfigurable computing framework for nanoscale devices
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Low-overhead defect tolerance in crossbar nanoarchitectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A hybrid nano-CMOS architecture for defect and fault tolerance
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Reliability aware yield improvement technique for nanotechnology based circuits
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
A defect/error-tolerant nanosystem architecture for DSP
ACM Journal on Emerging Technologies in Computing Systems (JETC)
NanoV: nanowire-based VLSI design
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
Discrete Applied Mathematics
Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability
Proceedings of the Conference on Design, Automation and Test in Europe
Computing with nanoscale memory: Model and architecture
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
Analysis of defect tolerance in molecular crossbar electronics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Defect-Aware Nanocrossbar Logic Mapping through Matrix Canonization Using Two-Dimensional Radix Sort
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Hybrid Redundancy for Defect Tolerance in Molecular Crossbar Memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Self-assembled nano-fabrication processes yield regular and reconfigurable devices. However, defect densities in this emerging nanotechnology are higher than those in conventional lithography-based VLSI. In this paper, we present a defect-tolerant design flow to minimize customized post-fabrication design efforts to be performed per chip. We also present a greedy O(n log n) mapping algorithm which makes the connection between defect-unaware design steps and the final defect-aware step. Experiments show that the results obtained by this algorithm are very close to the exact solutions.