Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A Case for CMOS/nano co-design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
DAC '84 Proceedings of the 21st Design Automation Conference
Large-signal two-terminal device model for nanoelectronic circuit analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Topology aware mapping of logic functions onto nanowire-based crossbar architectures
Proceedings of the 43rd annual Design Automation Conference
Decoding nanowire arrays fabricated with the multi-spacer patterning technique
Proceedings of the 46th Annual Design Automation Conference
Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability
Proceedings of the Conference on Design, Automation and Test in Europe
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
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In the coming decade, CMOS technology is expected to approach its scaling limitations. Among the proposed nan-otechnologies, nanowires have the edge in the size of circuits and logic arrays that have already been fabricated and experimentally evaluated. For this technology, logic-level design methodologies are being developed. The time has now come to develop automated tools for implementing VLSI designs using nanowires. In this paper, we discuss a design automation tool, called NanoV, to fulfill this need for nanowires. It is a complete logic-to-layout tool with built-in defect-aware steps since the defect levels in nanotechnologies are expected to be relatively high (between 1 to 10%). We are unaware of any other such comprehensive VLSI design tool for nanowires. We report area/delay/power results for various benchmarks implemented using our tool. We intend to make the tool available on the web.