Large-signal two-terminal device model for nanoelectronic circuit analysis

Authors:
Garrett S. Rose;Matthew M. Ziegler;Mircea R. Stan
Affiliations:
Electrical and Computer Engineering Department, University of Virginia, Charlottesville, VA;Electrical and Computer Engineering Department, University of Virginia, Charlottesville, VA;Electrical and Computer Engineering Department, University of Virginia, Charlottesville, VA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Year:
2004

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Abstract

As the nanoelectronics field reaches the maturity needed for circuit-level integration, modeling approaches are needed that can capture nonclassical behaviors in a compact manner. This paper proposes a universal device model (UDM) for two-terminal devices that addresses the challenge of correctly balancing accuracy, complexity, and flexibility. The UDM qualitatively captures fundamental classical and quantum phenomena and enables nanoelectronic circuit design and simulation. We discuss the motivation behind this modeling approach as well as the underlying details of the model. Furthermore, we present a circuit example of the model in action.