Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Large-signal two-terminal device model for nanoelectronic circuit analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Designing CMOS/molecular memories while considering device parameter variations
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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In recent years many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This paper describes the challenges faced in building crossbar array based molecular memory, and develops a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature. In particular, we discuss reading and writing such memory using CMOS and compiling a solution for easily reading device conductivity states (typically characterized by very small currents). Additionally, a metric is derived to determine the voltages for writing to the crossbar array. Simulation results, incorporating experimental device data, are presented using Cadence Spectre.