Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Large-signal two-terminal device model for nanoelectronic circuit analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Hybrid CMOS/Molecular Electronic Circuits
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Design approaches for hybrid CMOS/molecular memory based on experimental device data
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
CMOS/nano co-design for crossbar-based molecular electronic systems
IEEE Transactions on Nanotechnology
Nonphotolithographic nanoscale memory density prospects
IEEE Transactions on Nanotechnology
Design considerations for variation tolerant multilevel CMOS/Nano memristor memory
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Data-dependent statistical memory model for passive array of memristive devices
IEEE Transactions on Circuits and Systems II: Express Briefs
Design Considerations for Multilevel CMOS/Nano Memristive Memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A write-time based memristive PUF for hardware security applications
Proceedings of the International Conference on Computer-Aided Design
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In recent years, many advances have been made in the development of molecular scale devices. Experimental data shows that these devices have potential for use in both memory and logic. This article describes the challenges faced in building crossbar array-based molecular memory and develops a methodology to optimize molecular scale architectures based on experimental device data taken at room temperature. In particular, issues in reading and writing such as memory using CMOS are discussed, and a solution is introduced for easily reading device conductivity states (typically characterized by very small currents). Additionally, a metric is derived to determine the voltages for writing to the crossbar array. The proposed memory design is also simulated with consideration to device parameter variations. Thus, the results presented here shed light on important design choices to be made at multiple abstraction levels, from devices to architectures. Simulation results, incorporating experimental device data, are presented using Cadence Spectre.