Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions
Proceedings of the 32nd annual international symposium on Computer Architecture
Designing CMOS/molecular memories while considering device parameter variations
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Active control and digital rights management of integrated circuit IP cores
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
An Approach to Tolerate Process Related Variations in Memristor-Based Applications
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
Extracting secret keys from integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
History mechanism supported differential evolution for chess evaluation function tuning
Soft Computing - A Fusion of Foundations, Methodologies and Applications
Design Considerations for Multilevel CMOS/Nano Memristive Memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Hardware security has emerged as an important field of study aimed at mitigating issues such as piracy, counterfeiting, and side channel attacks. One popular solution for such hardware security attacks are physical unclonable functions (PUF) which provide a hardware specific unique signature or identification. The uniqueness of a PUF depends on intrinsic process variations within individual integrated circuits. As process variations become more prevalent due to technology scaling into the nanometer regime, novel nanoelectronic technologies such as memristors become viable options for improved security in emerging integrated circuits. In this paper, we describe a novel memristive PUF (M-PUF) architecture that utilizes variations in the write-time of a memristor as an entropy source. The results presented show strong statistical performance for the M-PUF in terms of uniqueness, uniformity, and bit-aliasing. Additionally, nanoscale M-PUFs are shown to exhibit reduced area utilization as compared to CMOS counterparts.