Designing CMOS/molecular memories while considering device parameter variations
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Overview of candidate device technologies for storage-class memory
IBM Journal of Research and Development
Phase-change random access memory: a scalable technology
IBM Journal of Research and Development
Characterizing flash memory: anomalies, observations, and applications
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Energy reduction for STT-RAM using early write termination
Proceedings of the 2009 International Conference on Computer-Aided Design
PCRAMsim: system-level performance, energy, and area modeling for phase-change ram
Proceedings of the 2009 International Conference on Computer-Aided Design
Nonvolatile memristor memory: device characteristics and design implications
Proceedings of the 2009 International Conference on Computer-Aided Design
Design considerations for variation tolerant multilevel CMOS/Nano memristor memory
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
How We Found The Missing Memristor
IEEE Spectrum
A write-time based memristive PUF for hardware security applications
Proceedings of the International Conference on Computer-Aided Design
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With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems by facilitating the implementation of multilevel logic. This work describes the design of such a multilevel nonvolatile memristor memory system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin for accurately reading and writing the data stored in a device are analyzed. Also analyzed are the nondisruptive read and write methodologies for the hybrid multilevel memristor memory to program and read the memristive information without corrupting it. This work showcases two write methodologies that leverage the best traits of memristors when used in either linear (low power) or nonlinear drift (fast speeds) modes. The system can therefore be tailored depending on the required performance parameters of a given application for a fast memory or a slower but very energy-efficient system. We propose for the first time, a hybrid memory that aims to incorporate the area advantage provided by the utilization of multilevel logic and nanoscale memristive devices in conjunction with CMOS for the realization of a high density nonvolatile multilevel memory.