Designing CMOS/molecular memories while considering device parameter variations
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Phase-change random access memory: a scalable technology
IBM Journal of Research and Development
Design Considerations for Multilevel CMOS/Nano Memristive Memory
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Non linear dynamics of memristor based 3rd order oscillatory system
Microelectronics Journal
Memristor-based memory: The sneak paths problem and solutions
Microelectronics Journal
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With technology migration into nano and molecular scales several hybrid CMOS/nano logic and memory architectures have been proposed thus far that aim to achieve high device density with low power consumption. The discovery of the memristor has further enabled the realization of denser nanoscale logic and memory systems. This work describes the design of such a multilevel memristor memory (MLMM) system, and the design constraints imposed in the realization of such a memory. In particular, the limitations on load, bank size, number of bits achievable per device, placed by the required noise margin (NM) for accurately reading the data stored in a device are analyzed.