Resistive non-volatile memory devices (Invited Paper)
Microelectronic Engineering
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
Design considerations for variation tolerant multilevel CMOS/Nano memristor memory
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Low-power dual-element memristor based memory design
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Practical approach to programmable analog circuits with memristors
IEEE Transactions on Circuits and Systems Part I: Regular Papers
An analogue model of the memristor
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
Non linear dynamics of memristor based 3rd order oscillatory system
Microelectronics Journal
Self-Adaptive Write Circuit for Low-Power and Variation-Tolerant Memristors
IEEE Transactions on Nanotechnology
Memristor Applications for Programmable Analog ICs
IEEE Transactions on Nanotechnology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved memristor-based relaxation oscillator
Microelectronics Journal
Memristor-based combinational circuits: A design methodology for encoders/decoders
Microelectronics Journal
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In this paper, we investigate the read operation of memristor-based memories. We analyze the sneak paths problem and provide a noise margin metric to compare the various solutions proposed in the literature. We also analyze the power consumption associated with these solutions. Moreover, we study the effect of the aspect ratio of the memory array on the sneak paths. Finally, we introduce a new technique for solving the sneak paths problem by gating the memory cell using a three-terminal memistor device.