Resistive non-volatile memory devices (Invited Paper)
Microelectronic Engineering
Compact models for memristors based on charge-flux constitutive relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Non linear dynamics of memristor based 3rd order oscillatory system
Microelectronics Journal
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
How We Found The Missing Memristor
IEEE Spectrum
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memristor-based memory: The sneak paths problem and solutions
Microelectronics Journal
Design investigation of nanoelectronic circuits using crossbar-based nanoarchitectures
Microelectronics Journal
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The crossbar architecture is viewed as the most likely path towards novel nanotechnologies which are expected to continue the technological revolution. Memristor-based crossbars for integrating memory units have received considerable attention, though little work has been done concerning the implementation of logic. In this work we focus on memristor-based complex combinational circuits. Particularly, we present a design methodology for encoder and decoder circuits. Digital encoders are found in a variety of electronics multi-input combinational circuits (e.g. keyboards) nowadays, converting the logic level '1' data at their inputs into an equivalent binary code at the output. Their counterparts, digital decoders, constitute critical components for nanoelectronics, mainly in peripheral/interface circuitry of nanoelectronic circuits and memory structures. The proposed methodology follows a CMOS-like design scheme which can be used for the efficient design and mapping of any 2^nxn (nx2^n) encoder (decoder) onto the memristor-based crossbar geometry. For their implementation, a hybrid nano/CMOS crossbar type with memristive cross-point structures and available transistors is elaborated, which is a promising solution to the interference between neighboring cross-point devices during access operation. Circuit functionality of the presented encoder/decoder circuits is exhibited with simulations conducted using a simulator environment which incorporates a versatile memristor device model. The proposed design and implementation paradigm constitutes a step towards novel computational architectures exploiting memristor-based logic circuits, and facilitating the design and integration of memristor-based encoder/decoder circuits with nanoelectronics applications of the near future.