A statistical performance simulation methodology for VLSI circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Diagnosis Method Using ΔIDDQ Probabilistic Signatures: Theory and Results
Journal of Electronic Testing: Theory and Applications
Behavioral Model of Analog Circuits for Nonvolatile Memories with VHDL-AMS
Analog Integrated Circuits and Signal Processing
Output Waveform Evaluation of Basic Pass Transistor Structure
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Elements of low power design for integrated systems
Proceedings of the 2003 international symposium on Low power electronics and design
Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Noise Library Characterization for Large Capacity Static Noise Analysis Tools
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A Technique for Designing Totally Self-Checking Domino Logic Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Simulating and Improving Microelectronic Device Reliability by Scaling Voltage and Temperature
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power reduction by varying sampling rate
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Implementation of MOSFET based capacitors for digital applications
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2m)
Journal of Electronic Testing: Theory and Applications
A hardware Memetic accelerator for VLSI circuit partitioning
Computers and Electrical Engineering
Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load
Integration, the VLSI Journal
Design principles for tamper-resistant smartcard processors
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Impact of MOSFET parameters on its parasitic capacitances
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Impact of MOSFET parameters on its parasitic capacitances
EHAC'07 Proceedings of the 6th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
A low-power reconfigurable logic array based on double-gate transistors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The threshold voltage of MOSFET and its influence on digital circuits
ACACOS'08 Proceedings of the 7th WSEAS International Conference on Applied Computer and Applied Computational Science
Impact of MOSFET's performance on its threshold voltage and its influence on design of MOS inverters
WSEAS Transactions on Systems and Control
The impact of MOSFET's physical parameters on its threshold voltage
MINO'07 Proceedings of the 6th conference on Microelectronics, nanoelectronics, optoelectronics
Combined circuit architecture for computing normal basis and montgomery multiplications over GF(2m)
Mobility '08 Proceedings of the International Conference on Mobile Technology, Applications, and Systems
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Scalable and Systolic Montgomery Multipliers over GF(2m)
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Sensitivity Analysis and Optimization Algorithm —– Based on Nonlinear Programming —–
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5fJ/stage PDP
Microelectronics Journal
Synthesizable time measurement and test scheme for SoC architecture
MINO'09 Proceedings of the 8th WSEAS international conference on Microelectronics, nanoelectronics, optoelectronics
Vulnerability modeling of cryptographic hardware to power analysis attacks
Integration, the VLSI Journal
Energy-aware probabilistic multiplier: design and analysis
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Nonlinear feedback system for an inverter-based ring oscillator
WSEAS Transactions on Circuits and Systems
Minimize the delay of parasitic capacitance and modeling in RLC circuit
Proceedings of the 2009 International Conference on Hybrid Information Technology
Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm
Computers and Electrical Engineering
EURASIP Journal on Embedded Systems
Low-complexity bit-parallel multipliers for a class of GF(2m) based on modified Booth's algorithm
International Journal of Computers and Applications
Delay and power management of voltage-scaled repeater driven long interconnects
International Journal of Modelling and Simulation
Particle swarm optimization based inverter design considering transient performance
Digital Signal Processing
Design and analysis of ultra low power true single phase clock CMOS 2/3 prescaler
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A 0.0018 mm2 frequency-to-digital-converter-based CMOS smart temperature sensor
Analog Integrated Circuits and Signal Processing
Low-voltage bulk-driven class AB four quadrant CMOS current multiplier
Analog Integrated Circuits and Signal Processing
Influence of the driver and active load threshold voltage in design of pseudo-NMOS logic
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
Role of driver and load transistor (MOSFET) parameters on pseudo-NMOS logic design
WSEAS Transactions on Circuits and Systems
Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Design research of the DES against power analysis attacks based on FPGA
Microprocessors & Microsystems
Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch
Microelectronics Journal
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Design of MRAM based logic circuits and its applications
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combined circuit architecture for computing normal basis and Montgomery multiplications over GF(2m)
International Journal of Autonomous and Adaptive Communications Systems
Reconfigurable Blocks Based on Balanced Ternary
Journal of Signal Processing Systems
A novel technique to reduce write delay of SRAM architectures
WSEAS Transactions on Circuits and Systems
9T full adder design in subthreshold region
VLSI Design
Scalable Gaussian Normal Basis Multipliers over GF(2m) Using Hankel Matrix-Vector Representation
Journal of Signal Processing Systems
Correlation power analysis attack of AES on FPGA using customized communication protocol
Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology
Memristor-based memory: The sneak paths problem and solutions
Microelectronics Journal
Low-power area-efficient wide-range robust CMOS temperature sensors
Microelectronics Journal
Ultra-low leakage arithmetic circuits using symmetric and asymmetric finFETs
Journal of Electrical and Computer Engineering
Static and dynamic analysis of organic and hybrid inverter circuits
Journal of Computational Electronics
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CMOS Digital Integrated Circuits: Analysis and Design is the most complete book on the market for CMOS circuits. Appropriate for electrical engineering and computer science, this book starts with CMOS processing, and then covers MOS transistor models, basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, BiCMOS circuits, I/O circuits, VLSI design methodologies, low-power design techniques, design for manufacturability and design for testability. This book provides rigorous treatment of basic design concepts with detailed examples. It typically addresses both the computer-aided analysis issues and the design issues for most of the circuit examples. Numerous SPICE simulation results are also provided for illustration of basic concepts. Through rigorous analysis of CMOS circuits in this text, students will be able to learn the fundamentals of CMOS VLSI design, which is the driving force behind the development of advanced computer hardware.Table of contents1 Introduction2 Fabrication of MOSFETS3 MOS Transistor4 Modeling of MOS Transistors Using SPICE5 MOS Inverters: Static Characteristics6 MOS Inverters: Switching Characteristics and Interconnect Effects7 Combinational MOS Logic Circuits8 Sequential MOS Logic Circuits9 Dynamic Logic Circuits10 Semiconductor Memories11 Low-Power CMOS Logic Circuits12 BiCMOS Logic Circuits13 Chip Input and Output (I/O) Circuits14 Design for Manufacturability15 Design for Testability