Synthesizable time measurement and test scheme for SoC architecture

Authors:
M. Amir Abas
Affiliations:
Centre for Research and Postgraduate Studies, University Kuala Lumpur, Malaysia
Venue:
MINO'09 Proceedings of the 8th WSEAS international conference on Microelectronics, nanoelectronics, optoelectronics
Year:
2009

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Abstract

This paper presents a Synthesizable high-resolution time measurement and test scheme for digital System on Chip (SoC) application namely Two-Delay Interpolation Method (TDIM). The scheme is designed to measure internal timing parameters in SoC architecture such as jitter, set-up and hold time, delay faults and etc. Simulation result shows the circuit is capable to measure as low as 5 ps timing interval and the range of measurement is programmable using programmable logic core in SoC. The small size of the design makes it eminently suitable for SoC applications, particularly when the accurate measurement of small time intervals are required; a need which is increasing as operational speeds tend toward 100GHz.