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ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Real-time dynamic voltage scaling for low-power embedded operating systems
SOSP '01 Proceedings of the eighteenth ACM symposium on Operating systems principles
Energy-conserving feedback EDF scheduling for embedded systems with real-time constraints
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
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RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
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ISWC '99 Proceedings of the 3rd IEEE International Symposium on Wearable Computers
Dynamic and Aggressive Scheduling Techniques for Power-Aware Real-Time Systems
RTSS '01 Proceedings of the 22nd IEEE Real-Time Systems Symposium
Dynamic voltage scaling for real-time multi-task scheduling using buffers
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Event-driven data acquisition and digital signal processing: a tutorial
IEEE Transactions on Circuits and Systems II: Express Briefs
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MobiCom '11 Proceedings of the 17th annual international conference on Mobile computing and networking
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nsdi'13 Proceedings of the 10th USENIX conference on Networked Systems Design and Implementation
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The rate at which a digital signal processing (DSP) system operates depends on the highest frequency component in the input signal. DSP applications must sample their inputs at a frequency at least twice the highest frequency in the input signal (i.e., the Nyquist rate) to accurately reproduce the signal. Typically a fixed sampling rate, guaranteed to always be high enough, is used. However, an input signal may have periods when the signal has little high frequency content as well as periods of silence. When the input signal has no perceptible high frequency components, the system can reduce its sampling rate, thereby reducing the number of samples processed per second, allowing the CPU speed to be scaled down without reducing output quality. This paper describes how to reduce power consumption in DSP applications by varying the amount of processing based on the input signal, and reports results of experiments with a prototype implementation. Experiments with a prototype show that when the system performs little processing, the added overhead of the variable sampling rate technique increased power consumption. When the system performs more processing, 18 FIR filters per frame, the power consumption was reduced to 40% of the power required for a static sampling rate, while not reducing sound quality