On optimum switch box designs for 2-D FPGAs
Proceedings of the 38th annual Design Automation Conference
How Much Logic Should Go in an FPGA Logic Block?
IEEE Design & Test
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Reconfigurable Architectures for General-Purpose Computing
Reconfigurable Architectures for General-Purpose Computing
Crossbar based design schemes for switch boxes and programmable interconnection networks
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices
ISMVL '06 Proceedings of the 36th International Symposium on Multiple-Valued Logic
Energy efficient and high speed on-chip ternary bus
Proceedings of the conference on Design, automation and test in Europe
Towards Reconfigurable Circuits Based on Ternary Controlled Analog Multiplexers/Demultiplexers
KES '08 Proceedings of the 12th international conference on Knowledge-Based Intelligent Information and Engineering Systems, Part III
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
An asynchronous ternary logic signaling system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Silicon-on-Insulator CMOS fabrication technologies are now available that offer a number of unique advantages including the availability of multiple simultaneous transistor thresholds. This paper proposes and analyzes a number of circuits for a reconfigurable array organization based on a balanced ternary logic system in which the logic set {驴驴1, 0,驴+驴1} maps directly to equivalent voltage levels {驴1V, 0V, +1V}. A number of low-power, high-speed components, such as a ternary buffer, flip-flop and look-up table, are described and simulated based on the characteristics of a commercially available silicon-on-sapphire process. A brief analysis indicates that the circuits will be capable of operating at the 22 nm technology node and beyond. A simple example of a Sigma-Delta Modulated FIR filter is mapped to the array and some preliminary estimates are made of its performance and area based on both 3-input and 4-input look-up tables. The simulated ternary array is shown to be capable of operating at clock speeds of more than 200 MHz such that it will readily support standard video bandwidths at useful over-sampling ratios.