Routing Architectures for Hierarchical Field Programmable Gate Arrays
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VPR: A new packing, placement and routing tool for FPGA research
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FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
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The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
A Mapping Methodology for Code Trees onto LUT-Based FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
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ACM Transactions on Embedded Computing Systems (TECS)
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ACM Journal on Emerging Technologies in Computing Systems (JETC)
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
The effect of multi-bit correlation on the design of field-programmable gate array routing resources
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Reconfigurable Blocks Based on Balanced Ternary
Journal of Signal Processing Systems
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The logic blocks of most modern FPGAs contain clusters of look-up tables and flip flops, yet little is known about good choices for several key architectural parameters related to these clusters. There are three basic questions: how many look-up tables should a cluster contain, how should the flexibility of FPGA routing change as the cluster size changes, and how many inputs should the programmable routing provide to each cluster? We first show that logic clusters require fewer inputs from the routing than current commercial FPGAs provide. Secondly, we show that for best area-efficiency the flexibility of FPGA routing should be significantly reduced as the cluster size is increased. Finally, we find that clusters containing between 1 and 8 look-up tables all provide reasonable area-efficiency, as long as the number of cluster inputs and the FPGA routing flexibility are chosen appropriately.