How Much Logic Should Go in an FPGA Logic Block?
IEEE Design & Test
The Video and Image Processing Emulation System VIPES
RSP '98 Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping
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One important algorithm for data compression is the variable length coding that often utilizes large code tables.Despite the progress modern FPGAs made, concerning the available logic resources, an efficient mapping of those tables is still a challenging task. In this paper, we describe an efficient mapping methodology for code trees onto LUT-based FPGAs. Due to an adaptation to the LUT's number of inputs, for large code tables a reduction of up to 40% of logic blocks is achievable compared with a conventional gate-based implementation.