Field-programmable gate arrays
Field-programmable gate arrays
On designing ULM-based FPGA logic modules
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Flexible FPGA architecture realized of general purpose SOG
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Boolean matching for large libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
Using Decision Diagrams to Design ULMs for FPGAs
IEEE Transactions on Computers
How Much Logic Should Go in an FPGA Logic Block?
IEEE Design & Test
On designing universal logic blocks and their application to FPGA design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Physical design methodologies for performance predictability and manufacturability
Proceedings of the 1st conference on Computing frontiers
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This paper presents a general methodology to determine the number of NPN functions of a programmable cell. This methodology was implemented in a tool called Programa_de_TV1 that is able to implement all NPN operations over n-input Lookup Tables. This work also shows a comparison between developed Universal Logic Gates (ULGs). One application of this technique is to select an appropriate programmable ULG to implement FPGA or Masked Programmable Architectures, according to some cost criteria. Another application of this tool is to help technology mapping into ULGs using an n-LUT mapper.