Technology mapping for electrically programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Universal logic gate for FPGA design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On Designing ULM-Based FPGA Logic Modules
On Designing ULM-Based FPGA Logic Modules
Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Series-parallel functions and FPGA logic module design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using BDDs to design ULMs for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Universal logic modules for series-parallel functions
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Universal switch-module design for symmetric-array-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Using Decision Diagrams to Design ULMs for FPGAs
IEEE Transactions on Computers
Generation of universal series-parallel Boolean functions
Journal of the ACM (JACM)
Design automation for mask programmable fabrics
Proceedings of the 41st annual Design Automation Conference
Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A tool for analysis of universal logic gates functionality
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
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In this paper, we give a method to design FPGA logic modules, based on an extension of classical work on designing Universal Logic Modules (ULM). Specifically, we give a technique to design a class of logic modules that specialize to a large number of functions under complementations and permutations of inputs, bridging of inputs and assignment of 0/1 to inputs. Thus, a lot of functions can be implemented using a single logic module. The significance of our work lies in our ability to generate a large set of such logic modules. A choice can be made from this set based on design criteria. We demonstrate the technique by generating a set of 471 8-input functions that have a much higher coverage than the 8-input cells employed by Actel's FP-GAs. Our functions can specialize to up to 23 times the number of functions that Actel functions can. We also show that by carefully optimizing these functions one can obtain multi-level implementations of them that have delays within 10% of the delays of Actel modules. We demonstrates the effectiveness of these modules in mapping benchmark circuits. We observed a 16% reduction in area and a 21% reduction in delay using our logic modules instead of Actel's on these circuits.