Universal logic gate for FPGA design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
On designing ULM-based FPGA logic modules
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
The triptych FPGA architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
An FPGA implementation and performance evaluation of the Serpent block cipher
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Using sparse crossbars within LUT
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Switching Theory for Logic Synthesis
Switching Theory for Logic Synthesis
How Much Logic Should Go in an FPGA Logic Block?
IEEE Design & Test
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Folding of logic functions and its application to look up table compaction
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
FPGA-Based System Design
Design, layout and verification of an FPGA using automated tools
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Improving soft-error tolerance of FPGA configuration bits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient canonical form for Boolean matching of complex functions in large libraries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact combinational logic synthesis and non-standard circuit design
Proceedings of the 5th conference on Computing frontiers
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Synthesis of networks of custom processing elements for real-time physical system emulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Exploration with upgradeable models using statistical methods for physical model emulation
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.00 |
This article introduces a novel lookup table (LUT) and its usage in the configurable logic block (CLB) architectures for SRAM-based field-programmable gate array (FPGA) architectures. The proposed CLB allows sharing of SRAM tables of LUTs among NPN-equivalent functions to reduce the size of memories used for storing the functions and also reduces the number of configuration bits required. We measured many different characteristics of FPGAs using our new CLB architecture, including area, delay, routing, and power requirements. We experimentally found that for many different FPGA architectures, CLBs can share one-fourth of their SRAM tables between two basic logic elements (BLEs), which reduced both power consumption and area without negatively affecting routing or wirelength, and there was only a negligible increase in critical path delay of 0.27%. Specifically, we find that FPGAs consisting of CLBs with 16 BLEs and 34 inputs can be implemented with eight normal SRAMs and four SRAMs shared between two BLEs, for an overall reduction of four out of sixteen SRAM tables per CLB. With this new CLB architecture, we measured an approximate reduction in overall power consumption of 2% and an estimated reduction in area of 3%.