Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of a SRAM-based field-programmable gate array—part II: circuit design and layout
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Automatic generation of FPGA routing architectures from high-level descriptions
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
The role of custom design in ASIC Chips
Proceedings of the 37th Annual Design Automation Conference
Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Architectures and algorithms for synthesizable embedded programmable logic cores
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Automatic transistor and physical design of FPGA tiles from an architectural specification
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Measuring the gap between FPGAs and ASICs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An 8x8 run-time reconfigurable FPGA embedded in a SoC
Proceedings of the 45th annual Design Automation Conference
Design flow for embedded FPGAs based on a flexible architecture template
Proceedings of the conference on Design, automation and test in Europe
Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs
Journal of Signal Processing Systems
Automatic design of reconfigurable domain-specific flexible cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic reconfiguration architectures for multi-context FPGAs
Computers and Electrical Engineering
Regular fabric for regular FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Minimum energy operation for clustered island-style FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Physical design exploration of 3D tree-based FPGA architecture
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately 50 to 200 person years from architecture definition to tape-out for a new FPGA family. Such a lengthy development time is necessary because the process is primarily done manually. Simplifying and shortening the design process would be advantageous since it could reduce the time to market for new FPGAs while also enhancing architecture explorations. One way to accomplish this is through automation and, in this paper, we describe our efforts to automate the entire process by making use of a previously developed set of tools that assist in the creation of the repeatable FPGA tile [25]. Our aim is to demonstrate the feasibility of a CAD flow that uses an input FPGA architecture description to generate a layout that can be sent for fabrication. We prove the feasibility of this proposition by actually designing and fabricating a complete FPGA. Initial functional testing of the FPGA appears promising but is inconclusive at this time. Through this architecture to layout process, we investigate the issues that are faced in the architecture selection, circuit design, layout and verification of such an automatically produced FPGA. We found that there are significant savings in design time. As well, we demonstrate that we can produce a layout using automated tools that is only 36% larger than a commercial FPGA device layout. Given the significant time savings and the relatively minor area penalty, we feel that this work demonstrates that automated layout of FPGAs is practical and advantageous.