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ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
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Proceedings of the 27th annual international symposium on Computer architecture
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FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
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FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of Interconnection Networks for Programmable Logic
Design of Interconnection Networks for Programmable Logic
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
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ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
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SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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This paper presents a novel architecture combining an application specific instruction set processor (ASIP) core and an application domain specific embedded FPGAs (eFPGAs) used as flexible accelerator for the ASIP. The eFPGA is based on a parametrisable architecture template optimised for arithmetic oriented applications. It was designed as a physically optimised VLSI-macro using a flexible design methodology also sketched in this paper. Quantitative comparisons of the eFPGA with a commercial standard FPGA show significant improvements in energy, area and timing delays. Simulations of the new ASIP-eFPGA architecture have been conducted using a model based approach to evaluate its efficiency. The results show that power- and area-efficiencies similar to an FPGA can be achieved for the flexible ASIP-eFPGA while preserving the flexibility of a software programmable processor.