Discrete cosine transform: algorithms, advantages, applications
Discrete cosine transform: algorithms, advantages, applications
MPEG Video Compression Standard
MPEG Video Compression Standard
Digital Video: An introduction to MPEG-2
Digital Video: An introduction to MPEG-2
FPGA and CPLD Architectures: A Tutorial
IEEE Design & Test
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
IEEE Design & Test
Field-Programmable Custom Computing Machines - A Taxonomy -
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
TriMedia CPU64 Application Development Environment
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
TriMedia CPU64 Application Domain and Benchmark Suite
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
TriMedia CPU64 Design Space Exploration
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
MPEG Macroblock Parsing and Pel Reconstruction on an FPGA-Augmented TriMedia Processor
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs
Journal of Signal Processing Systems
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This paper presents a TriMedia processor extended with three reconfigurable designs for entropy decoding (ED), inverse quantization (IQ), and two-dimensional (2-D) inverse discrete cosine transform (IDCT), and assesses the performance gain that is provided by such extensions when performing MPEG2-compliant pel reconstruction. We first describe an extension of the TriMedia architecture, which consists of a multiple-context field programmable gate array (FPGA)-based reconfigurable functional unit (RFU), a configuration unit managing the reconfiguration of the RFU, and their associated instructions. Then, we address the computation of the ED, IQ, and 2-D IDCT tasks, and propose to provide reconfigurable hardware support for a variable-length decoder that can decode two symbols per call (VLD-2), an inverse quantizer that can dequantize four coefficients per call (IQ-4), and an 1-D IDCT (1-D IDCT). The most important aspects concerning the implementation of the FPGA-mapped VLD-2, IQ-4, and 1-D IDCT units, as well as the organization of the software routines calling these FPGA-mapped computing units are outlined. Experimental results indicate that by configuring each of the VLD-2, IQ-4, and 1-D IDCT units on a different FPGA context, and by activating the contexts as needed, the FPGA-augmented TriMedia can perform MPEG2-compliant pel reconstruction with an average speed-up of 1.4 × over the standard TriMedia.