An Architectural Overview of the Programmable Multimedia Processor, TM-1
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Design for Debug: Catching Design Errors in Digital Chips
IEEE Design & Test
A Heterogeneous Multiprocessor Architecture for Flexible Media Processing
IEEE Design & Test
Eclipse: Heterogeneous Multiprocessor Architecture for Flexible Media Processing
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Design of multi-tasking coprocessor control for Eclipse
Proceedings of the tenth international symposium on Hardware/software codesign
Scheduling Analysis Integration for Heterogeneous Multiprocessor SoC
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Test Infrastructure Design for the Nexperia" Home Platform PNX8550 System Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding
Proceedings of the conference on Design, automation and test in Europe - Volume 3
The future of multiprocessor systems-on-chips
Proceedings of the 41st annual Design Automation Conference
Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A scalable, clustered SMT processor for digital signal processing
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
Pel reconstruction on FPGA-augmented TriMedia
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Strategies for the integration of hardware and software IP components in embedded systems-on-chip
Integration, the VLSI Journal - Special issue: IP and design reuse
Mapping and configuration methods for multi-use-case networks on chips
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Power/performance hardware optimization for synchronization intensive applications in MPSoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
HIBI Communication Network for System-on-Chip
Journal of VLSI Signal Processing Systems
An efficient synchronization technique for multiprocessor systems on-chip
MEDEA '05 Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture
Journal of VLSI Signal Processing Systems
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Access Regulation to Hot-Modules in Wormhole NoCs
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
FlexWAFE - a high-end real-time stream processing library for FPGAs
Proceedings of the 44th annual Design Automation Conference
A high-end real-time digital film processing reconfigurable platform
EURASIP Journal on Embedded Systems
JTRES '07 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Predator: a predictable SDRAM memory controller
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Towards understanding architectural tradeoffs in MEMS closed-loop feedback control
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Elastic Flow in an Application Specific Network-on-Chip
Electronic Notes in Theoretical Computer Science (ENTCS)
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ICLP '08 Proceedings of the 24th International Conference on Logic Programming
Available task-level parallelism on the Cell BE
Scientific Programming - High Performance Computing with the Cell Broadband Engine
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Multi-processor programming in the embedded system curriculum
ACM SIGBED Review
Application development with the FlexWAFE real-time stream processing architecture for FPGAs
ACM Transactions on Embedded Computing Systems (TECS)
A platform-based design framework for joint SW/HW multiprocessor systems design
Journal of Systems Architecture: the EUROMICRO Journal
Mapping stream programs onto heterogeneous multiprocessor systems
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Automatic task generation for the multi-level computing architecture
PDCS '07 Proceedings of the 19th IASTED International Conference on Parallel and Distributed Computing and Systems
Synthesis algorithm for application-specific homogeneous processor networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Architecture and Code Optimization (TACO)
A real-time Java chip-multiprocessor
ACM Transactions on Embedded Computing Systems (TECS)
Heterogeneous multi-core platform for consumer multimedia applications
Proceedings of the Conference on Design, Automation and Test in Europe
SCMP architecture: an asymmetric multiprocessor system-on-chip for dynamic applications
Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies
A3MAP: architecture-aware analytic mapping for networks-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design and implementation of an operating system for composable processor sharing
Microprocessors & Microsystems
Efficient synchronization for embedded on-chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capacity optimized NoC for multi-mode SoC
Proceedings of the 48th Design Automation Conference
Execution migration in a heterogeneous-ISA chip multiprocessor
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
A3MAP: Architecture-aware analytic mapping for networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
ACM Transactions on Embedded Computing Systems (TECS)
Application space exploration of a heterogeneous run-time configurable digital signal processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Auto-design systematic methodology of cluster MPSoC for multiple concurrent applications
International Journal of Computer Applications in Technology
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Viper is a complete system-on-a-chip solution from Philips Semiconductors for next-generation digital television and digital video applications. It incorporates Philips' intellectual-property reuse methodology in addition to standard hardware and software building blocks.